A Fully Autonomous SSHIC Interface Circuit With Configurable Multi-Step Bias-Flip for Piezoelectric Energy Harvesting

This brief presents a piezoelectric energy harvesting interface circuit with a multi-step bias-flip strategy to boost the energy extraction capability. The optimized parallel synchronized switch on inductor and capacitor (SSHIC) technique is adopted. Except for the external inductor and capacitors, the proposed interface circuit is designed for fully integrated control without any external adjustment during the bias-flip process. Moreover, the steps for bias-flip can be configured flexibly, and the circuit can work even without an inductor. The interface circuit has been designed and implemented with 0.18-
${\mu }\text{m}$
CMOS technology. With the 5-step bias-flip SSHIC topology and a 1-mH inductor, the simulated whole current dissipation is 106 nA, the measured maximum flipping efficiency is 90.3%, and the measured maximum power efficiency improvement is 642% compared to the ideal full bridge rectifier (FBR).