Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation

Recently, many computing-in-memory (CIM) systems based on non-volatile devices have been implemented well. However, they perform poorly in high bit-width processes due to device access latency and energy cost. In this brief, we present an in memory fully non-volatile parallel-prefix adder(PPA) based on CIM system for 2T1MTJ spin-orbit torque magnetic random access memory(SOT MRAM). Unlike traditional CMOS circuits, CIM prefers uniform logic gates(only AND or OR gates at each logic level). Thus, to calculate the output of each logic level, traditional AND/OR logic is substituted with MAJORITY/NOT logic. We also propose an optimized logical mapping strategy that requires one write operation instead of continuous write operations at each write-back stage, which maximizes the performance benefits of the PPA.