An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC

This paper presents a continuous-time sigma-delta modulator (CTSDM) with a voltage-controlled-oscillator-based (VCO-based) integrating quantizer. A background replica-based calibration technique is proposed to alleviate the impact of the process, voltage supply, and temperature (PVT) variations on the tuning characteristic and current consumption of the VCO-based quantizer. Matching between the replica VCO and the main VCO in the proposed calibration is not needed. A latency-free background calibration technique is also proposed to eliminate the distortions caused by the DAC mismatch. The prototype VCO-based CTSDM is fabricated in a 40 nm CMOS and achieves SNDR/SFDR/DR of 76.4 dB/91.7 dBc/79.6 dB, respectively, within a 50 MHz bandwidth (BW) at 1.6 GHz sampling frequency. The measured SNDR varies within ±1 dB over a temperature range of $0\sim 80~^{\circ }\text{C}$ and a voltage supply variation of ±10%, across different tested samples. The power consumption is 18.1 mW, achieving a Schreier Figure of Merit (FoMS) of 170.8 dB.

I. Introduction

The continuous-time sigma-delta modulator (CTSDM) is widely used in wireless communication systems [1]–[4]. With a CTSDM followed by a digital decimator, a CTSD analog-to-digital converter (ADC) can be implemented. Compared with a discrete-time (DT) ADC, the CTSDM implementation relaxes the design requirement of the front-end driver and anti-alias filter due to its easily-driven resistive impedance and inherent anti-alias feature. A relatively high resolution within wide signal bandwidth (BW) (MHz) can be achieved in the CTSDM, thanks to the noise-shaping and oversampling properties and the relaxed settling requirement. Recently, the CTSDM has become more favored in a multimode wireless communication system [4]–[9], e.g., 2/3/4/5G reconfigurable receiver.