A Low-Voltage-Driven High-Voltage SRAM Pixel Circuit for Power Reduction in a Digital Micro-Display Panel

A new SRAM-based pixel circuit is presented for use in a high-voltage digitally-driven pixel array in a micro-display panel. The pixel circuit is based on the standard 6T SRAM structure, but uses two more transistors of which gate dc-bias is controlled to adjust the pull-up strength of the inverters in the SRAM. This allows the pixel circuit to be operated with low-voltage row- and column-line signals while holding the stored logic in a high-voltage level. As a result, power and area of the pixel driving circuits are greatly reduced. The added two transistors do not necessitate area overhead if the pixels are to be individually separated with rectangular shape, which is true in many cases. To verify proper operation and power reduction efficacy of the proposed SRAM pixel circuit, a simple $100\times 200$ digital pixel array, together with row- and column-line drivers, is implemented using a 0.13-$\mu \text{m}$ CMOS technology and 1.5-V/3.3-V supplies. The measurement results show that, with the optimum bias for the two added transistors, total power dissipation including pixel array and driver power can be reduced by about as much as 78 %, which is very close to the theoretical limit of 79 % (= (1.5/3.3)²).

I. Introduction

Traditional approach for driving pixels in many flat panel displays, such as liquid crystal displays and organic-light-emitting diode (OLED) displays, are based on an analog manner with the use of digital-to-analog converters (DACs) [1]–[5]. This is due to limited operating speed of the thin-film transistors used for the pixel circuits, and large loadings by the long row and column lines and a great number of pixel circuits on each line. However, when it comes to realization of a very small-sized displays, such as liquid-crystal-on-silicon (LCoS) or OLED-on-silicon micro-displays, digital pixel driving can be a good alternative since it can easily take advantage of high-speed CMOS transistors on silicon backplane, and capacitive loadings on row and column lines are relatively small due to the reduced panel size [6]–[8].