A 0.34 mm2 1 Gb/s Non-Coherent UWB Receiver Architecture With Pulse Enhancement and Double PLL Clock/Data Packet Recovery

This paper presents a compact impulse-radio ultra-wide band non-coherent receiver architecture for high data rate wireless neural recordings from active high-density CMOS-probes. The system is capable of receiving, synchronizing, and demodulating a continuous on-off keying pulse stream at 1 Gb/s and 4 GHz center frequency using an active area of 0.34 mm
²
and a single 31.25 MHz crystal reference. An asynchronous threshold energy detector, including a pulse enhancement baseband with an all-digital back-end, recovers incoming transmitter clock (CDR) and acquires packet synchronization based on a data-aided mechanism (DPR). Results shows that a prototype of the receiver integrated in a 130 nm CMOS process recovers synchronization in 30 ns. The system includes I/O output buffers and driver logic at 1.8 V supply operating at 1 GHz on a 50 $\Omega $ load and crystal oscillator. Overall, it consumes 115 pJ/pulse, while the receiver core only consumes 12 pJ/pulse. This paper presents the receiver architecture, and experimental results show a sensitivity of -38 dBm at 10
^-3
packet error ratio.