Synthesis of Ternary Logic Circuits Using 2:1 Multiplexers

Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present a novel synthesis technique to implement ternary logic circuits using 2:1 multiplexers. Initially a methodology, which transforms a ternary logic function into a ternary-transformed binary decision diagram, is presented. This methodology is the basis for the synthesis algorithm that is used to synthesize various ternary functions using 2:1 multiplexers. Results for various ternary benchmark functions indicate that the proposed algorithm results in circuits that have, on an average 79%, and up to 99% fewer transistors when compared with the most recent 3:1 multiplexer-based algorithm available in the literature. Synthesized circuits have been implemented using carbon-nanotube field-effect transistors and simulated in HSPICE.

I. Introduction

Synthesis of digital circuits, with various parameter constraints, has been actively pursued over the past few decades. This has led to development of several synthesis tools that transform high-level hardware descriptions into logic circuits. These tools have been employed in development of circuits with large complexity e.g. application specific integrated circuits [1], general-purpose processor designs [2]. However, with the emergence of new computing paradigms (reversible computing [3], multi-valued logic (MVL) computing [4]) coupled with emerging devices (carbon-nanotube field effect transistor (CNFET) [5], Quantum-dot gate field effect transistor (qFET) [6]etc), there is a need for new synthesis algorithms and tools that take advantage of special characteristics of emerging devices and computing paradigms.