A Novel Low-Effort Demodulator for Low Power Short Range Wireless Transceivers

This paper presents a novel demodulator architecture for short distance communication application with low effort, which is low-power low-cost while achieving robust and sufficient performance. Compared to other architectures, power consumption and design complexity are significantly reduced. Practical issues such as image interference, group delay and frequency offset are compensated and calibrated in the proposed architecture. Simulation results show that with the proposed techniques the receiver gains significant robustness against image interference, and also higher immunity to the noise and the frequency mismatches. This demodulator circuit is fully integrated in 130 nm CMOS technology, and occupies 0.36 mm
²
area with 3.4 mW of power consumption.