A 0.22-μW Single-Bit VCO-Based Time-Domain Sensor-to-Digital Front-End With Reduced Supply Sensitivity

Future energy harvesting systems require ultra-low supply sensor interfaces operating at sub-0.4 V. Time-based sensor-to-digital interfaces, though compatible with ultra-low supply, are highly sensitive to inherent mismatch in the current-controlled ring oscillators (CCRO) especially in a multibit architecture. Contrary to a multi-bit sensor interface, this work realizes a single-bit system replacing the multi-phase CCRO with a nanoWatt current-controlled relaxation oscillator (CCRxO) and thus obviating the significant delay cell mismatch in the CCROs. In addition, we propose a time domain calibration loop (TDCL) to mitigate the high signal-to-noise and distortion ratio (SNDR) sensitivity related to the K_VCO variation with respect to supply. A pulse-biasing circuit is proposed for fast settling of the internal nodes and facilitate quick switching between calibration and data conversion modes. The proposed closed-loop single-bit VCO-based sensor-to-digital front-end with TDCL was fabricated in 180 nm CMOS technology. Operating under 0.35 V, the chip consumes a total power consumption of $0.22~\mu \text{W}$ only with a SNDR of 63.2 dB. The SNDR variation is measured to be only 1.7 dB with more than 50% supply variation validating the effectiveness of the proposed TDCL.