Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem

This paper presents an area and power-efficient variable-size DCT architecture for HEVC application. We develop a reconfigurable and scalable shift-and-add unit (SAU) embedded in our 1D-DCT architecture by leveraging Muxed-MCM problem with the aim of increasing the hardware reusability in the arithmetic units, while reducing the hardware cost. The key idea behind the proposed architecture is the fact that in most of the times (≈90%) the lower point DCTs are performed when the higher point SAUs remain unused. Accordingly, we focus on merging the SAUs of lower point DCTs into the higher point DCTs to compute multiple lower point DCTs in parallel as well as processing any combination of transform sizes. The experimental results show that the proposed folded and fully-parallel 2D-DCT architectures achieve the best hardware cost by 45% and 30% reduction in gate count, respectively, amongst the existing architectures. Moreover, power saving of 55% and 32% can be achieved for the proposed folded and fully-parallel architectures, respectively, where they can process 60 fps of 4K and 30 fps of 8K UHD video sequences in 300 MHz operating frequency.