I. Introduction
High speed chip-to-chip communication links have seen a tremendous growth to the order of terabits per second aggregate data rates to support transmission, storage, and retrieval of high-volume data. In order to thrive in the deep sub-micron technologies, there is an increased complexity in I/O signaling circuits to leverage maximum data rate per unit area for efficient area utilization of I/O pins [1]. Consequently, there is an inherent need for high throughput density for an interconnect technology due to cost-prohibitive nature of multiple parallel interconnects. The idea of increasing throughput density demands for an increase in bandwidth density (data rate per unit area per pin) [1]–[5].