A 100-Gbps 4-Lane Transceiver for 47-dB Loss Copper Cable in 28-nm CMOS

A 103.13-Gbps 4-lane transceiver for copper cable applications was fabricated in 28-nm CMOS technology. The transceiver can transmit 103.13-Gbps data through 4-lane 47-dB-loss channels. To achieve this result, ISI should be suppressed; equalization allocation of a four-tap FFE, a CTLE with a low-frequency equalizer and a DFE is optimized with the proposed tap-based auto equalization. In addition, SNR degradation should be suppressed as much as possible to receive a small signal through a large loss channel. Here, a sub-mV dynamic DC offset canceller and a DFE with a bias controlled tap slicer are proposed. The DC offset canceller reduces DC offset of the CTLE to less than 1 mV. The DFE with a bias controlled tap slicer has an input sensitivity finer than 1.2 mV0p, which improves the SNR at the slicer's input and reduces the dead zone of CDR phase detector to less than 1.7 ps. The transceiver consumes 403 mW from a 0.9 V and 1.5 V supply per lane, which includes 1/4 of the power consumption of the PLL and 1/8th the power consumption of the common block.