A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output

This paper presents a novel compute-in-memory (CIM) macro, which mainly consists of three modules: input generator, 9T1C-SRAM CIM array and charge-integration-count output (CICO) circuit. For the input generator, it can achieve the pulse-width modulation mapping scheme without counts, leading to a small area overhead. For the CIM array, one row-cascade current mirror circuit instead of a bias voltage source is shared by all CIM cells in one row. And in each CIM cell, its multiply result is characterized by the charge on its capacitor. Based on the charge-sharing principle, the accumulated result is represented by the charge (
$\text{Q}_{\text {CBL}}$
) on the charge-bit-line (CBL). In this way, the voltage on the CBL is limited regardless of the number of rows of the CIM array, allowing the large-scale CIM array. For the CICO circuit, it is proposed to quantify the
$\text{Q}_{\text {CBL}}$
without the ADC, aiming to achieve high area efficiency. With the 14nm FinFET design kit, the design specification of the proposed CIM macro is introduced in detail and its performance is evaluated. Simulation results show that the proposed CIM macro can achieve 4–1370 TOPS/W energy efficiency with IN/W/OUT precision of 6/1/6b and 98.48%/84.56% test accuracy on MNIST and CIFAR-10.