Noise Model of Large-Format Readout Integrated Circuit for Infrared Focal Plane Array

With the upscaling of the pixel format and the downscaling of the pixel pitch of infrared focal plane arrays (FPAs), the demand for ultra-low-noise design is increasing drastically. Existing methods of noise modelling lack transistor-level analysis and are unable to provide directly effective guidance for circuit design because of extremely complicated mathematical expressions. In this work, a comprehensive noise model of large-format readout integrated circuit (ROIC) is presented, for the first time elucidating the noise mechanism with a full research framework, including transistor-, circuit-, block-, and chip-level analysis. By utilizing a novel approximation method, simplified analytical formulas with high accuracy are obtained for flicker noise and other noise. These simplified formulas clear up the confusions of how the various functional circuit blocks influence noise performance. Moreover, based on the presented noise model, the impacts of crucial parameters on FPA noise are analyzed in detail, and strategies regarding the trade-off between the signal-to-noise ratio (SNR) and other aspects of performance are proposed for low-noise design. Taking an astronomical application with a very long integration time as an example, the calculated results show that an ultralow noise of
${5}{\,e^{-}}$
can be achieved by leveraging the above approaches.