SRAM cell with better read and write stability with Minimum area

This paper describes a novel SRAM architecture to improve read and write stability. Read stability is enhanced by increasing β ratio to 4 and write stability is enhanced by storage node charging and discharging through two transistors. The proposed 8T SRAM architecture is compared with Conventional 6T, decoupled 8T SRAM cell and 10T SRAM cell. 6T SRAM cell required 584.1mV word line voltage to write data into a cell at 1.2V supply voltage whereas the proposed SRAM cell requires only 512.8mV, leakage power is close to leakage power of 6T SRAM cell.