Instruction Profiling Based Fetch Throttling for Wasted Dynamic Power Reduction

In superscalar processors the throughput of the early pipeline stages will impose an upper bound on the throughput of all the subsequent stages. Therefore, to achieve high performance, maximum instruction fetch bandwidth is maintained. This leads to higher power dissipation that often is wasted due to aggressive fetching of instruction cache. To address this problem, this paper implements fetch throttling based on instruction profiling. Instruction profile indicates how likely the instructions are to be stalled in each pipeline stages. The knowledge of the probable residence of the instructions at different stages can enable throttling mechanism to reduce wasted dynamic power with minimal performance penalty. In this paper, we propose fetch throttling based on instruction profiling for top 10 instructions that contribute to frequent pipeline stalls. Simulation results show that instruction profiling based fetch throttling improves average energy efficiency in the range of 24.36-39.70% for an average performance degradation of 5.3412.20% at different levels of fetch throttling.