Junctionless-FET device fabrication using silicon etching in NH4OH solution: device behaviour according to etching time

Junctionless-Field-Effect-Transistor (JL-FET) devices were fabricated with Silicon-On-Insulator (SOI) technology. The device channel area was thinned down to nanometer-scale by silicon etching in a solution of NH
₄
OH with the area to be exposed define using optical lithography and silicon oxide etching in HF buffer solution. The hardmask was stripped and dopant diffusion on a Phosphorus saturated furnace was carried out to achieve the dopant concentration necessary. The gate oxide was silicon oxide grown thermally in a dry environment. The electrical contacts were fabricated using optical lithography, silicon oxide etching in HF solution, aluminum sputtering and lift-off. The electrical contacts were annealed in forming gas (H
₂
+ N
₂
) for 10 minutes. Gate metal was titanium nitride deposited using sputtering and defined using optical lithography and lift-off. A layer of aluminum was deposited with the titanium nitride to protect it against oxidation. Some advantages were observed on this updated process. The outlines of the etched area are observable with optical microscopy in a dark field filter, making process confirmation easy. The same outlines are exposed for the majority of fabrication time, making atomic force microscopy (AFM) possible. Also, pseudo-MOS measurements are possible even before the gate metallization, which gives insight on the fabrication process and quality. The measurements on devices fully fabricated showed increasing control of the gate bias on the drain current, which is in agreement to JL-FET predictions, although these behave a gated resistor due to their negative threshold voltage. This happens because the VOH is high even for low a VGS, making the VDS needed to achieve saturation mode unmanageable. The electrical contacts were ohmic in nature and showed that the dopant diffusion process is compatible with JL-FET fabrication. Overall, these devices show that the JL-FET, and other nanometer-scaled structures, are possible to achieve using the channel thinning in NH
₄
OH solution silicon etching.