An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training

The aim of neuromorphic computing system is to implement the computational power and efficiency of the human brain. Computing-in-memory (CIM) is a promising and energy-efficient way to perform intensive computations, whose structure is similar to human brain synapse. A 8.78TOPS/W biologically-inspired neuromorphic computing system for pattern recognition based on CIM architecture is presented in this work. The proposed system supports on-chip training with energy-efficient bio-plausible spike-timing-dependent plasticity (STDP) rule and performs multiply-and-accumulate (MAC) computations inside SRAM array during inference, which greatly reduces the energy consumption. Simulated in 65-nm technology, the proposed system achieves good performance and energy efficiency for pattern recognition. The total energy consumption of training and classifying per image of the proposed system is 0.20 nJ. And the proposed spiking neural network (SNN) just consumes 0.074mW at 1.0V with the throughput of 2.5M images/s in inference phase.

I. Introduction

Many state-of-the-art systems for machine learning [1]–[2] can achieve good performance on various recognition tasks, such as image classification, speech recognition and tracking detecting. But the systems are limited by memory in terms of the energy they require and the performance they can achieve [3]. For example, deep neural networks (DNNs) bring huge performance improvement, but it consumes a lot of computational and memory resources [2]. Furthermore, it causes long latency and high power consumption due to heavy data movement [4]. Therefore, many researchers study how to reduce the data movement and computational power consumption of neural network. Recently, the emerging architecture that performs computations inside the memory array, also called computing-in-memory (CIM), is widely used in DNNs to reduce data movement across the memory layers [3]–[6]. While most researchers have focused on designing inference engines, many tasks such as adapting to changing environments in real-time have shown that on-chip training could be extremely important.