System Co-Design Inclusive of Connectivity for 3DIC and Wafer-Level Packaging

With the drive towards adding more functionality on a system and the era of artificial intelligence and IoT in play, the semiconductor industry has responded by moving away from the Moore's law approach of shrinking the chip and instead focusing on 3D integration of dies and/or packages. While by itself this poses significant challenges in the manufacturing and testing of these new architectures, there is also a need to address the issues this creates for the design flow itself. The key difference in design flow is the increasing number of iterations, not only of designs, but also the combination of designs. One die may be used across multiple packages or PCBs. This necessitates the need to create flows which are cognizant of variations. Added to this is the complexity of having to tackle new architectures like fan out wafer-level packaging or 3D ICs. The classical methodology of passing the design information from the between chip/package and package/PCB teams will be much too restrictive, costly and potentially the key to faster time-to-market product. This paper explores the solution to this the complex system connectivity optimization challenge and further demonstrates a way to track and verify connection changes throughout the design process.