IBIS model generation and validation of CMOS Buffer

With the increasing demand to improve the time to market, the semiconductor industry has always had a need for a faster design simulation standard. The traditionally available transistor-level SPICE models are highly efficient for the simulation of digital circuits but have a high time complexity making it difficult to model an interface with predictable bit error rates. So in order to reduce the time complexity of simulation and estimate the bit error rates accurately, the IBIS (Input/output Buffer Information Specification) standard is used. The IBIS models also protect the Intellectual Properties involved in the design. In this paper, an IBIS model is created for a CMOS (Complementary Metal Oxide Semiconductor) logic inverting buffer on the transmitter side and validated against its SPICE (Simulation Program with Integrated Circuit Emphasis) model.