Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map

In this paper, we implemented a lightweight reconfigurable pseudo-random number generator (PRNG). The map generates discrete-time chaotic signals. The chaotic oscillator requires two map circuits to generate chaotic signals. The design is reconfigurable because two map circuits have two bifurcation parameters which can be leveraged to generate multiple random sequences. The design of the PRNG utilizes two chaotic oscillators, analog mux, 10 bit ADC, 2 bit shift register and an XOR gate. The circuit has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The estimated power consumption of the circuit is 2.12 mW and the area overhead is 0.132 mm
²
. The throughput of the proposed PRNG is 100 MS/s. The proposed PRNG can be used for security applications in IoT devices which requires circuits with less area and power overhead. The PRNG design passes all the tests in NIST SP 800-22 test suite.