Power Supply Noise Rejection Improvement Method in Modern VLSI Design

In modern integrated circuits the technology scaling and supply voltages values decreasing caused degradation of noise immunity of VLSI ICs. Therefore, the rejection of the noises in the power rails become a huge challenge considering the fact of area and power consumption requirements of the modern ICs. This paper presents a power supply noise rejection improvement method based on the combination of MOS (metal oxide semiconductor) and MOM (metal oxide metal) devices as capacitors which purpose is the decrease of dependency of decoupling capacitor capacitance on PVT (process, voltage, temperature) variations. According to the achieved results design of decoupling capacitors based on the proposed method decreases the total occupied area by 1,5 times without degradation of the noise immunity of the circuits.