A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs

A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔI
_DLIN
) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (V
_D
), gate (V
_G
) and body (V
_BB
) biases is modeled. The framework is also capable of modeling the channel length (L
_CH
) and gate-oxide thickness (T
_OX
) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔI
_DLIN
modeling.