Implementing VESA Display Stream Compression Encoder in FPGAs

In this paper, an architecture for implementing VESA DSC image compression standard in FPGAs is proposed. DSC uses a very small 3-pixel wide coding unit that restricts the HW architecture of the prediction part to only three pipeline stages. The proposed architecture optimizes the pipeline distribution and performs algorithmic optimizations in order to reduce the critical path inside the prediction modes of DSC. It achieves 62 MHz and requires 18595 slices on Virtex 7 spl. It can process full HD (1920×1080) 4:4:4 images at 30 frames per second and full HD 4:2:2 or 4:2:0 images at 60 frames per second, while it has sub-line latency.