3.3V ESD Clamp structure susceptibility towards Pseudo Latch Up in 22nm FDSOI

An unexpected failure occurred during Latch-Up test of a 22FDSOI chip which had 3.3V general purpose I/Os implemented using 1.8V compliant devices. The high supply current flowing was not a real LU failure but due to triggering of RC clamp during negative current injection on nearby I/Os. The pseudo Latch-Up is presented along with methods to ensure robustness of 3.3V clamp design structures.