A Novel Triple Inverter Design for CMOS Clocks and Oscillators

Single inverter gate CMOS oscillator designs have been used for decades based on the CMOS technology of the time. While a single inverter gate can deliver very good performance dependent on the application, it presents design limitations due to parameter trade-offs of transconductance, output impedance, and bias current. This paper introduces a novel CMOS sustaining amplifier design that significantly increases the design flexibility beyond what a single inverter can provide. It uses a three-stage inverter with the center inverter incorporating negative feedback to allow for a wide range of transconductance with wide operational bandwidth. High transconductance can provide operation for high-resistance resonators and or resonators that have significant activity dips [1]. This design is resistant to parasitic oscillations seen with high transconductance sustaining amplifiers. An equation and model describing the circuit transconductance is derived and accurately determines this circuit gain using a small number of circuit parameters. Given a desired transconductance, this new amplifier operates with lower power and higher output impedance than an equivalent single inverter. Engineers at Sandia National Laboratories have fabricated and implemented this type of design with approximately 20 mS of transconductance at frequencies of 50 MHz and has been applied to frequencies up to 100 MHz.