A High Performance Implementation of Quasi Delay Insensitive Booleans Functions

Digital circuit design demands critical requirements such as power consumption, robustness, performance, etc. when it is implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features aiming to solve these requirements. An important class of asynchronous paradigm is the so-called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for those kinds of applications because they are robust to noise, to temperature variations, to wire and gate delays and to supply voltage variation, having also low electromagnetic emissions. QDI combinational circuits are designed as function blocks whose indicatability shows the robustness of the circuit communication with the environment. This paper presents two architectures based on basic gates and C elements as also an approach to the synthesis of the QDI function blocks. The two new architectures were prototyped in FPGAs (Field Programmable Gated Array) devices, applied in a set of benchmarks and compared with other architectures of the literature. Our proposal shows respectively a gain of up to 18.6%, 53.1%, 40.7% and 51.8% in latency, number of LUTs and power, dynamic and static, respectively.