A 1GSPS Open-Loop Track and Hold Circuit with 68dB SNDR in 65nm CMOS

This paper presents a 1GSPS open-loop track and hold circuits with high linearity in a 65nm CMOS process. High linearity is achieved by the analysis of the source of nonlinearity and the use of some linearize techniques: source follower buffer, gate-bootstrapping switches, signal feedthrough cancellation, source degeneration technique. As a result, the THC provides higher than 65 dB SFDR, and higher than 68 dB SNDR with input frequencies up to 631MHz.