A Novel TDC Scheme: Combinatorial Gray Code Oscillator Based TDC for Low Power and Low Resource Usage Applications

In common digital electronics design practice, combinatorial loop is less preferable, especially in the multi-bit cases. An exception of multi-bit feedback system that is allowed to be implemented in combinatorial loop is the Gray code sequence generator. The Gray code sequence generator runs by itself without being driven by an external clock. It steps through Gray code sequence significantly faster than the Gray code counter under the same silicon technology. In high energy physics experiments, it is necessary to find a low resource usage and low power TDC (Time-to-Digital-Converter) scheme for high channel count detectors. A Gray code oscillator based TDC is a good candidate for such a scheme. In this paper, we describe our work of design and implementation of a TDC based on combinatorial Gray code oscillator in a Xilinx Kintex-7 FPGA (Field-Programmable Gate Array). The implementation and test results are presented. The test result shows that the TDC using only 8 logic elements is able to reach a RMS precision of 160 ps for time difference measurements of a single pulse. The single pulse measurement precision can be further improved to 51 ps with the weighted average scheme using data from the same TDC channels captured by 4 consecutive system clock edges.