Front-End Digitization for Fast Imagers

Decreasing the size of CMOS technology nodes plays a key role in embedding more functionality in modern imagers. Digitization of the data close to the origin of the sensor signal provides large margins in time and amplitude, making them substantially robust against noise, crosstalk and power supply fluctuations. Moreover, early digitization offers advantages of in-pixel data processing and system power reduction, but on the cost of pixel area increase. Experiences of two readout ASICs facilitating in-pixel digitization are summarized here. The first ASIC for single photon counting utilizes an 8-bit ADC on pixel level. The second ASIC is used to read out a digital silicon photomultiplier intended for particle tracking. It benefits from the digital property inherent of the sensor's avalanche multiplication. Both ASICs are fabricated in the GF 130-nm CMOS technology and flip-chip techniques are used for the hybrid integration of sensor and readout ASIC. The demand for higher pixel granularity asks for larger data transmission bandwidth, more sophisticated power concepts and the extension of 3-D stacking technologies.