High Speed Multipliers using Counters based on Symmetric Stacking

High speed multipliers are essential in all computational units such as Arithmetic Logic Unit(ALU), Multiply Accumulate Unit and Digital Signal Processing (DSP) applications. In general, the performance of any DSP system is limited by its multiplication performance. Hence, the speed and power efficient multiplier algorithms are highly demanded in present scenario. In this Paper, high speed multipliers are designed by using binary counters based on symmetric stacking. In this work, 16-bit Wallace tree multiplier is considered for the analysis using conventional counters and symmetric stacking-based counters. Further, the performance is compared in terms of delay, area. All the blocks used in this work are programmed using Verilog HDL and they are Synthesized using Xilinx.