Cu Microstructure of High Density Cu Hybrid Bonding Interconnection

The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits (3D IC) using chip partitioning and wafer-to-wafer bonding have been acknowledged as the next generation semiconductor stacking technology because of smaller form factor, higher density integration and higher performance compared to same-node devices. Wafer-to-wafer bonding is widely used in stacked CMOS image sensor, that is, the bonding between pixel and logic wafer, and this technology has the potential to apply other semiconductor devices. Cu-Cu hybrid bonding has achieved by simultaneous wafer bonding of metal (Cu-Cu) and dielectric materials. In this study, it is investigated on the microstructure of Cu pad for Cu-Cu bonding after post-electroplating and post-bonding annealing process. The Cu grain size distribution and orientation are analyzed with different anneal temperature, which is applied on electroplated Cu, and with additional heat treatment as post-bonding process. The effect of pad size as well as the position within pattern array on Cu microstructure is also studied as the bonding pad is required smaller and smaller size for high density bonding. After Cu-Cu bonding, the cross-section analysis of bonding interface is carried out to see inter-diffusion of Cu atoms across the opposite Cu pad. Cu-Cu hybrid bonding is applied to test vehicle having the daisy chain of 2.4 million. The electrical resistance is measured before and after thermal stress and the Cu-Cu bonding interface is confirmed as robust structure.