Inductive Links for 3D Stacked Chip-to-Chip Communication

This paper focusses on an experimental inductive link study based on S-parameter measurements up to 67 GHz for 3D stacked chip to chip communication. This is complemented by a calibrated HFSS model for coupling between two chips that is then extended to stacks with up to eight chips. This approach allows for a complete analysis of the inductive link mechanisms between stacked chips and the impact of different parameters. Moreover, a circuit level assessment of the inductive link for a transmitter circuit has been performed using FinFET technology.