Highly Compact RF Transceiver Module Using High Resistive Silicon Interposer with Embedded Inductors and Heterogeneous Dies Integration

Silicon interposers are providing interesting alternatives to organic packages for the fabrication of complex system in package (SIP) modules in particular for RF application. Among the advantages of this technology are the capability to fabricate fine pitch redistribution layers and to embed inside the interposer some high quality passive elements very close to the active chips resulting in a highly integrated solution. To keep the technology at a reasonable cost these last add-on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of a high resistive silicon interposer conceived for hosting a functional RF SIP transceiver including a Front End Module (FEM), a Dual Band Dual Mode Power Amplifier working at 400 and 900 MHz and some embedded planar and 3D inductors. The interposer consists in symmetrical stack with one thick level of copper RDL on each side of the 200 μm thin HR silicon substrate and connected with through silicon via-last (TSV-last). The inductors are built with no additional metallization level. For the inductors development, a dedicated test vehicle was first designed to study different designs including planar spirals and 3D solenoids and torus. Simulation work was first carried out for dimensioning the structures to target inductance values in the range of 0.5 to 10 nH and high quality factor greater than 20. We present the process used for the fabrication, in particular the realization of the thick copper RDL layers on both sides of the interposer and the of the TSV-last module. Physical characterization are presented showing the integrity and the good control of the technology. DC and RF electrical measurements assess the performances achieved for the different inductor variants exhibiting low resistance, constant inductance up to 5 GHz and factor of quality higher than 30. The functional RF transceiver SIP module will be then presented. The architecture is an extremely compact multi chip module composed of four actives CMOS chips (VGA, VCO, modulator and the PA) stacked by flip chip with Cu/SnAg μbumps on the HR silicon interposer and surrounded by a hundred of passive SMD components. With this technology the footprint of the module is reduced by a factor of 2 in comparison with the same module made on a μPCB substrate. The signals and ground are fed through the thick copper RDL lines and the TSVs from LGA pads present on the backside of the interposer for assembly on a test board. Different design configurations are made on the same wafer that include some version using only SMD inductors and some using 2.5 and 3D inductors in order to compare the corresponding performances. Other test structures are also present like filters and individual inductors for DC and RF characterization. We will finally present the resulting performances obtained from this SIP integration.