FinFET IO Device Performance Gain with Heated Implantation

FinFET doping via implantation at room temperature could result in Fin damage within the Fin body and degrade Fin device performance. Heated implantation techniques are developed to address the detrimental effects on devices caused by the damage. The wafer can be maintained at specific temperature on the platen while the implantation is in progress. The wafer substrate temperature can affect the implant caused damage cascade by enhancing or retarding the interstitial and vacancy (IV) recombination process. In this paper, the heated implantation technique was applied to IO FinFET LDD formation. Since IO devices operate at relative high voltage and electrical field which could result in higher leakage, multiple implants were used to tailor the junction to mitigate so-called band to band tunneling (BTBT) leakage. A scaled FinFET with tight pitch demands higher implanted dose to form a suitable junction for leakage control. However, increased dose induces more damage to the Fin which leads to device degradation. Therefore, implant damage should be mitigated to achieve device performance gain by LDD implant. We will present bare wafer SIMS profile studies and device results along with TCAD simulations, comparing room temperature and heated temperature implants. 14nm FinFET device studies showed 3-5% device gain with heated implant and it demonstrated heated implant technique can bring device benefits for further scaled FinFET.