Evaluation of Analog Circuit Performance for Ferroelectric SOI MOSFETs considering Interface Trap Charges and Gate Length Variations

The performance of ferroelectric SOI (FE-SOI) analog circuits considering the impact of interface trap charge (N
_it
) and gate length (L
_g
) variations are analysed for the first time. For FE-SOI MOSFETs, the discharging time (t
_s
), on resistance (R
_on
) of switch circuit, and output current (I
_out
) of current mirror show superior immunity to N
_it
and L
_g
variations compared to the SOI counterparts. FE-SOI MOSFETs show significant improvements in discharging time (-78% and -31%) at V
_dd
=0.4V and 1V compared to SOI MOSFETs due to the negative capacitance induced voltage amplification and higher drive current. Besides, FE-SOI switch circuit exhibits lower R
_on
and better R
_on
flatness which suppresses distortion for audio and signal processing applications. FE-SOI current mirror with larger output resistance shows better current matching (smaller I
_out
/I
_ref
) than SOI one, and comparable mirroring performance compared to the stacked SOI current mirror. Therefore, FE-SOI current mirror can significantly reduce the circuit complexity and area penalty while maintaining adequate mirroring accuracy.