A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration

This paper presents a high speed nonbinary 2-then3b/cycle SAR ADC with background offset calibration. By exploiting comparators with two input paths, multiplication and subtraction can be performed in comparators instead of extra DAC array, resulting in reduced area and power overhead. Pseudo asynchronous clock as well as boundary detection mapping scheme are utilized to suppress metastability. Furthermore, a self background offset calibration, without external inputs or DAC configuration, is implemented on chip to ensure PVT robustness. A 7-bit prototype SAR ADC fabricated in 40nm LP CMOS achieves 39.7dB SNDR at 900MS/s sampling rate and consumes 2.6mW, resulting in a Nyquist FoM of 36.6fJ/conv-step.