A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells

This paper presents a two-way time-based folding ADC that uses a passive pulse shrinking (PPS) technique to quantize fine time resolution with a purely passive R-C network. A time folding, and subtraction circuit is introduced to further increase the dynamic range of the ADC without adding more PPS cells. The prototype is implemented in 65nm CMOS and achieves 32.5dB SNDR at 5.001GHz input frequency with the sampling rate of 10GS/s while consuming 29.7mW and occupying an area of 0.015mm
²
, yielding an FOM of 86fJ/c-step.