TAMPER: Thermal Assistant Method to Improve Write PERformance in STT-RAM Memories

TAMPER presents a novel write-energy-aware driver circuit to decrease Write Error Rate (WER). Complementary metal-oxide-semiconductor, abbreviated as CMOS are vulnerable to serious shortage in designing parameters such as leakage power, scalability, and vulnerability to soft errors for designing a high dencity circuits. Spin Transfer Torque RAM (STT-RAM) is known as the most promising candidate for replacement the current memory technologies according to non-volatility characteristic. write errors occur in this technology primarily because of the process variation phenomenon. Write errors associated with different current densities is one of the major drawbacks of STT-RAM, also seen elsewhere in similar devices and a possible solution to such is presented and discussed in TAMPER. A thermal assistant write driver circuit is proposed, which has the ability to eliminate the process variation on write operation. By using this thermal assistance the asymmetric behavior of Magnetic Tunneling Junction (MTJ) over writing two states “0” and “1” decrease, which leads to reduce the time and energy needed for the writing operation. Experimental simulations have been done and compared with existing methodologies to validate the design. Power, performance, and WER enhancement by optimization in physical characteristics of transistors is achieved with on average 38.68% improvement of write time latency along with a 1.41% decrease in area.