Duty-Cycle Correction Circuit For High Speed Interfaces

DCC circuit is designed for high speed interfaces such as Universal serial bus (USB) and Peripheral component interconnect express (PCIe). It finds the duty-cycle variations from nominal value by a differential amplifier detection circuit output state and corrects thru the negative feedback loop. The DCC has improved stability, correction range and operating frequency as compared with mixed-signal and all-digital DCCs. For the simulation have been used 14nm FINFET technology, have been implemented CML-CMOS buffer with positive feedback which made attainable the output duty cycle correction to 50 ± 0.05% over the input duty-cycle range of 20-80% for 5-10GHz. 10GHz operating frequency and 0.8 V supply voltage DCC consumes 1.8 mW. The disadvantage of the proposed DCC is settling time increasing by 15% compared to analog feedback DCC without positive feedback CML-CMOS buffer.