Design and Analysis of High Performance Multiplier Circuit

Multiplier is of the most important blocks of many VLSI application. So, it is required to design high performance multiplier to boost up the performance of those circuits and systems. In this work, a high performing Multiplier has been designed by using Wallace tree algorithm. The multiplier has been designed in three modules. Initially partial products are generated followed by partial products processing. Finally, final addition is computed in the 3rd module. Partial products have been generated by using AND gates. Partial products are computed by using Wallace tree logarithm. Final addition has been done by fast adder. The performance of the proposed multiplier circuit is evaluated by using 90nm CMOS technology at the Synopsys tool. The performance of the same is compared conventional multiplier circuits. The performance of the proposed adder has been found to be satisfactory.