Damping of inter-area mode oscillations by $\pmb{H}_{\infty}$ Loop shaping technique based UPFC controller

This paper presents a procedure for the robust design of an SDC for a UPFC device for damping inter-area mode oscillations in the large power system. The controller is designed by H
_∞
loop shaping technique using LMI. The controller is designed for modified New England test system which includes a UPFC. The input signals to the controller are obtained from PMUs located at an important buses of the test system. For deciding the best control signal as input to the controller, residue analysis was carried out. The minimum damping ratio (10%) is ensured with by adding pole placement objective in the controller design. The robustness of the UPFC WADC is accessed via nonlinear time domain simulations for various contingency conditions like line fault, line outage, and load shedding. The performance of the UPFC W ADC is found satisfactory for such contingency conditions.