A Simplified Model for Approximating the Vias in the Thermo-Mechanical Simulation of Metal-Oxide-Semiconductor Structures

Finding a qualitative model to study the thermo-mechanical effects inside the Metal-Oxide-Semiconductor power Integrated Circuits (MOS power IC's) is needed even from the design stage of such devices. The high number of geometry details contained by these devices, especially at the level of the metallization system, rise difficulties in the Finite Element Method (FEM) analyze, thus some simplifications are needed. In this paper a simple method of geometry details reduction is proposed, in order to eliminate some geometrical details such as vias between two different metal layers. While the geometry details are simplified, the thermo-mechanical behavior is assessed on a simple Double-Diffused MOS (DMOS) substructure with an open source software (Code_Aster) based on FEM. In order to understand the influence of vias at the metallization level, temperature and strain distributions are compared for three different cases with vias, no-vias and equivalent materials properties block respectively. The no vias model approach capture with less computational effort and good accuracy the thermal induced metal deformation.