Efficient Energy Delivery and Dynamic Control for SOC High Power Supply

In this paper, we discuss a chip-package integration and miniaturization for managing high power supply demand of microprocessor. To deliver the high performance system with granular features, significant improvement of physical design of power supply network were implemented. There was also a redesign to the hierarchy power management including clock gating, voltage pre-core regulation and dynamic frequency scaling. The optimized performance metrics of the wafer integrations are presented with measured implications and simulations. The new generation microprocessor is demonstrated with a highly configurable power solution of high power density and fast response that increases the energy efficiency and peak performance.

Introduction

Power delivery and dissipation limits constitute a major constraint in achieving the market-driven performance targets of next-generation high end systems. While technology scaling allows increased device and core count at near-historical growth rates, operational frequency and single-thread performance growth has slowed considerably because of the power wall. An energy efficient SoC power delivery scheme need switch capacitor converter and integrated voltage regulator for fast responsive power network. A major challenge in the power delivery design is to achieve sufficient integration and minimization of key components, while still maintaining high power efficiency and fast switching capability. The circuit blocks shrink and the embedded LC passives should scale sequentially in the manner of Moore’s law. This enables SoC to continue delivering a compelling power performance benefit to support the scaling process.