Optimize of High-k Capping Layer Loss Thickness in DPRM Process to Avoid Vth Shift

As a high-k capping layer, TiN thickness affects the work function in NMOS, which will affect the flat band voltage and cause V
_th
shift. When the high-k metal gate device is fabricated by the gate-last method, a new process named dummy poly removal (DPRM) is derived. The thickness of TiN is affected in DPRM process inevitably. In this paper, we propose a method to adjust the thickness of TiN to avoid V
_th
shift from the etching view, which is that the TiN loss of NMOS is optimized by changing the flow rate of NF
₃
gas in etching poly step under the condition of electron cyclotron resonance (ECR) plasma source etching machine, and complete the device electrical verification.