Investigation on LDMOS Characteristics of Layout Dependence in FinFET Technology

The characteristics of a laterally diffused metal oxide semiconductor (LDMOS) with different layout structures is investigated based on 14nm FinFET technology. The layout dependences of the breakdown voltage (BVDS), linear drain current (Idlin), on state resistance (Ron), drain cut-off current (Idoff), and Idlin degradation were studied to optimize FinFET performance with improved device structure. The overlap between N-drift region and metal gate (Lw) has a crucial impact on the breakdown voltage, Idlin, and Ron. The BVDS is 4% lower, and Ron reduced about 15% for 1x channel length device at Lw=1.8x than Lw=1x. Idoff is increased with the increase of Lw. The BVDS, Idoff, and Idlin degradation caused by hot carrier injection (HCI) are also investigated by the different overlap length of P-type well and N-drift region (Lo). With increase of Lo, the BVDS is increased and Ioff is decreased. The Idlin degradation is reduced 1.8 times by the optimization of Lo.