A High Efficiency N Channel Single Poly OTP Cell Structure in Standard CMOS Process

A high efficiency N channel single poly OTP (One time programmable memory) cell structure is proposed in this paper. The cell consists of one NMOS transistor and one MOS capacitor. NLDD implant is blocked in the NMOS area of the cell to improve program efficiency and reduce channel length. The NMOS gate and the capacitor top plate is the same polysilicon gate. It is electrical isolated and works as “floating gate”. The capacitor bottom plate is the lateral diffusion region of NLDD. It works as the “control gate”. In comparing with traditional structure the cell size shrinks 40% and can be easily integrated into a standard CMOS process without additional mask.