High Speed DPWM for Digital Power Converter Controller

This study proposes a new architecture of digital pulse width modulator (DPWM) for power converter with digital control loop. The described architecture is based on a new counter-based concept. The new approach requires two counter loops: a slow big one and a fast small one. The fast counter loop is driven by a clock generated with a digital implemented ring oscillator, which is located on the chip close to the DPWM block. The slow counter measures the switching period. The fast counter provides the high precision duty cycle. The proposed concept was examined on the buck converter with 10-32V input voltage range, 5.8V output voltage, 2MHz switching frequency, 4.7uH filter inductance and 22uF filter capacitance. A proportional-integral-derivative (PID) controller was taken as a control loop feedback mechanism. To maintain the optimal duty cycle resolution of the DPWM the 576MHz ring oscillator was required. The proposed architecture improves the static characteristics of the converter while there is no impact on the dynamic characteristics. The results are showing that the output voltage ripple can be improved by 15% with absolute improvements of 14.4mV and the output current ripple can be reduced by 220mA for 1.1A load current. The ring oscillator frequency deviation of -20% to +30% has a small impact on the functional efficiency of the DPWM.