Short-Circuit Ruggedness Analysis of SiC JMOS and DMOS

To prevent the degradation caused by Bessel plane dislocation and improve the characteristics of body diode in silicon carbide MOSFETs, Schottky barrier diode integrated MOSFET has been developed by many researchers. One of those structures was named JMOS which exhibits much higher chip area efficiency. In this paper, the relationship between short-circuit withstanding time and VGS is presented. After this, a series of comparison between conventional DMOS and JMOS are executed, which covered a single pulse short-circuit event and a repetitive short-circuit test. The result shows that short-circuit withstanding capability of JMOS is still good enough but slightly less than that of DMOS, which means both devices could handle over 3 micro-seconds of short-circuit duration with no failure occurs. With repetitive short-circuit stress in this work, the electrical characteristics have been measured on D.U.T. by monitoring the test waveform after finished 10,000 times of pulses. In this experiment, no significant degradation has been detected after repetitive short-circuit stress. Furthermore, the failure mechanism of JMOS may be different from conventional DMOS and this will be discussed in this work.