Experimental Study on the Effect of Recessed Gates in Drain STI Regions of nLDMOSFETs

The introduction of a recessed gate into a shallow trench isolation (STI) section used as an insulating film in a drift region of an nLDMOSFET is a well-known means of improving the trade-off between the on-resistance (R
_sp
) and the off-state breakdown voltage (BV
_off
), as well as reducing hot-carrier injection (HCI) degradation in the maximum substrate current ( I
_submax
) condition. Moreover, a drain multi-finger STI nLDMOSFET structure in which an STI section and a silicon surface section in the drift region are repeated in the channel width direction can improve the R
_sp
-BV
_off
trade-off. However, the effect of combining these structures on a silicon substrate has not been sufficiently investigated. In the present study, the effect of recessed gates on R
_sp
, BV
_off
, and HCI degradation in two types of nLDMOSFET are investigated.