A Novel Highly Reliable 12T SRAM Bitcell Design

This paper presents a novel highly reliable dual port 12T static random access memory (SRAM) bitcell. Compared with the state-of-the-art soft-error-tolerant bitcells and the traditional 6T, the proposed 12T exhibits much larger read noise margin (RSNM), and also saves 85.4% read access time on average, making it much suitable for high-speed highly reliable applications.